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Chapter 1 Device Overview (MC9S12XDP512V2)
MC9S12XDP512 Data Sheet, Rev. 2.11
98 Freescale Semiconductor
1.6.2 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states.
1.6.2.1 I/O Pins
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
1.6.2.2 Memory
The RAM array is not initialized out of reset.
Vector base + $7E $3F Autonomous periodical interrupt (API) I bit VREGAPICTRL (APIE)
Vector base + $7C $3E Reserved
Vector base + $7A $3D Periodic interrupt timer channel 0 I bit PITINTE (PINTE0)
Vector base + $78 $3C Periodic interrupt timer channel 1 I bit PITINTE (PINTE1)
Vector base + $76 $3B Periodic interrupt timer channel 2 I bit PITINTE (PINTE2)
Vector base + $74 $3A Periodic interrupt timer channel 3 I bit PITINTE (PINTE3)
Vector base + $72 $39 XGATE software trigger 0 I bit XGMCTL (XGIE)
Vector base + $70 $38 XGATE software trigger 1 I bit XGMCTL (XGIE)
Vector base + $6E $37 XGATE software trigger 2 I bit XGMCTL (XGIE)
Vector base + $6C $36 XGATE software trigger 3 I bit XGMCTL (XGIE)
Vector base + $6A $35 XGATE software trigger 4 I bit XGMCTL (XGIE)
Vector base + $68 $34 XGATE software trigger 5 I bit XGMCTL (XGIE)
Vector base + $66 $33 XGATE software trigger 6 I bit XGMCTL (XGIE)
Vector base + $64 $32 XGATE software trigger 7 I bit XGMCTL (XGIE)
Vector base + $62 — XGATE software error interrupt I bit XGMCTL (XGIE)
Vector base + $60 — S12XCPU RAM access violation I bit RAMWPC (AVIE)
Vector base+ $12
to
Vector base + $5E
Reserved
Vector base + $10 — Spurious interrupt — None
1
16 bits vector address based
2
For detailed description of XGATE channel ID refer to XGATE Block Guide
Table 1-8. Interrupt Vector Locations (Sheet 3 of 3)
Vector Address
1
XGATE
Channel ID
2
Interrupt Source
CCR
Mask
Local Enable