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Chapter 4 Port Integration Module (S12XDP512PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
204 Freescale Semiconductor
4.3.2.9 Port E Data Register (PORTE)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
0x0008 (PRR)
76543210
R
PE7 PE6 PE5 PE4 PE3 PE2
PE1 PE0
W
Alt.
Func.
XCLKS
or
ECLKX2
MODB
or
TAGHI
MODA
or
RE
or
TAGLO
ECLK
EROMCTL
or
LSTRB
or
LDS
R/
W
or
WE
IRQ XIRQ
Reset 000000—
1
1
These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
pin values.
—
1
= Unimplemented or Reserved
Figure 4-11. Port E Data Register (PORTE)
Table 4-12. PORTE Field Descriptions
Field Description
7–0
PE[7:0]
Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include
mode select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (
TAGHI,
TAGLO), Read/Write (R/W), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ.
When not used for any of these specific functions, Port E pins 7–2 can be used as general purpose I/O and
pins 1–0 can be used as general purpose inputs.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.
Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.