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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.11
646 Freescale Semiconductor
Write: For transmit buffers, anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for
receive buffers.
Reset: Undefined (0x00XX) because of RAM-based implementation
14.3.3.1 Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
14.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping
Register
Name
Bit 7 654321Bit 0
IDR0
0x00X0
R
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
W
IDR1
0x00X1
R
ID2 ID1 ID0 RTR IDE (=0)
W
IDR2
0x00X2
R
W
IDR3
0x00X3
R
W
= Unused, always read ‘x’
Figure 14-24. Receive/Transmit Message Buffer — Standard Identifier Mapping
Module Base + 0x00X1
76543210
R
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
W
Reset: xxxxxxxx
Figure 14-25. Identifier Register 0 (IDR0) — Extended Identifier Mapping
Table 14-26. IDR0 Register Field Descriptions — Extended
Field Description
7:0
ID[28:21]
Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.