Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description
MC9S12XDP512 Data Sheet, Rev. 2.11
596 Freescale Semiconductor
13.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
13.3.2.1 IIC Address Register (IBAD)
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
Register
Name
Bit 7 654321Bit 0
0x0000
IBAD
R
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
0
W
0x0001
IBFD
R
IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
W
0x0002
IBCR
R
IBEN IBIE MS/
SL Tx/Rx TXAK
00
IBSWAI
W
RSTA
0x0003
IBSR
R TCF IAAS IBB
IBAL
0SRW
IBIF
RXAK
W
0x0004
IBDR
R
D7 D6 D5 D4 D3 D2 D1 D0
W
= Unimplemented or Reserved
Figure 13-2. IIC Register Summary
Offset Module Base +0x0000
76543210
R
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
0
W
Reset 00000000
= Unimplemented or Reserved
Figure 13-3. IIC Bus Address Register (IBAD)