Chapter 9 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
446 Freescale Semiconductor
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with
the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
CSL
Logical Shift Left with Carry
CSL
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
old
^ RD[15]
new
C: Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Source Form
Address
Mode
Machine Code Cycles
CSL RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 0 1 0 P
CSL RD, RS DYA 0 0 0 0 1 RD RS 1 0 0 1 0 P
C
RD
C C C
n bits
C
n