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Chapter 16 Serial Peripheral Interface (S12SPIV4)
MC9S12XDP512 Data Sheet, Rev. 2.11
734 Freescale Semiconductor
16.4.7.4 Reset
The reset values of registers and signals are described in Section 16.3, “Memory Map and Register
Definition”, which details the registers and their bit fields.
• If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit
garbage, or the byte last received from the master before the reset.
• Reading from the SPIDR after reset will always read a byte of zeros.
16.4.7.5 Interrupts
The MC9S12XDP512 only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The
following is a description of how the MC9S12XDP512 makes a request and how the MCU should
acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent.
The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.
16.4.7.5.1 MODF
MODF occurs when the master detects an error on the
SS pin. The master SPI must be configured for the
MODF feature (see Table 16-3). After MODF is set, the current transfer is aborted and the following bit is
changed:
• MSTR = 0, The master bit in SPICR1 resets.
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the
interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing
process which is described in Section 16.3.2.4, “SPI Status Register (SPISR)”.
16.4.7.5.2 SPIF
SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does
not clear until it is serviced. SPIF has an automatic clearing process, which is described in
Section 16.3.2.4, “SPI Status Register (SPISR)”.
16.4.7.5.3 SPTEF
SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear
until it is serviced. SPTEF has an automatic clearing process, which is described in Section 16.3.2.4, “SPI
Status Register (SPISR)”.