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Chapter 5 Clocks and Reset Generator (S12CRGV6)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 305
5.5 Resets
This section describes how to reset the MC9S12XDP512, and how the MC9S12XDP512 itself controls the
reset of the MCU. It explains all special reset requirements. Since the reset generator for the MCU is part
of the CRG, this section also describes all automatic actions that occur during or as a result of individual
reset conditions. The reset values of registers and signals are provided in Section 5.3, “Memory Map and
Register Definition”. All reset sources are listed in Table 5-14. Refer to MCU specification for related
vector addresses and priorities.
5.5.1 Description of Reset Operation
The reset sequence is initiated by any of the following events:
• Low level is detected at the RESET pin (external reset)
• Power on is detected
• Low voltage is detected
• Illegal Address Reset is detected (see S12XMMC Block Guide for details)
• COP watchdog times out
• Clock monitor failure is detected and self-clock mode was disabled (SCME=0)
Upon detection of any reset event, an internal circuit drives the
RESET pin low for 128 SYSCLK cycles
(see Figure 5-25). Since entry into reset is asynchronous, it does not require a running SYSCLK. However,
the internal reset circuit of the MC9S12XDP512 cannot sequence out of current reset condition without a
running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional
SYSCLK cycles depending on the internal synchronization latency. After 128 + n SYSCLK cycles the
RESET pin is released. The reset generator of the MC9S12XDP512 waits for additional 64 SYSCLK
cycles and then samples the RESET pin to determine the originating source. Table 5-15 shows which
vector will be fetched.
Table 5-14. Reset Summary
Reset Source Local Enable
Power on Reset None
Low Voltage Reset None
External Reset None
Illegal Address Reset None
Clock Monitor Reset PLLCTL (CME = 1, SCME = 0)
COP Watchdog Reset COPCTL (CR[2:0] nonzero)