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Chapter 20 Debug (S12XDBGV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
822 Freescale Semiconductor
information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format
for loop1 mode is the same as that of normal mode. Whilst tracing from XGATE or CPU only, in normal
or loop1 modes each array line contains data from entries made at 2 separate times, thus in this case the
DBGCNT[0] is incremented after each separate entry. In all other modes, DBGCNT[0] remains cleared
while the other DBGCNT bits are incremented on each trace buffer entry.
XGATE and S12X_CPU COFs occur independently of each other and the profile of COFs for the 2 sources
is totally different. When both sources are being traced in Normal or Loop1 mode, for each single entry
from one source, there may be many entries from the other source and vice versa, depending on user code.
COF events could occur far from each other in the time domain, on consecutive cycles or simultaneously.
If a COF occurs in one source only in a particular cycle, then the trace buffer bytes that are mapped to the
other source are redundant. Info byte bit CDV/XDV indicates that no useful information is stored in these
bytes. This is the typical case. Only in the rare event that both XGATE and S12X_CPU COF cycles
coincide is a valid trace buffer entry for both made, corresponding to the first line for mode "Both
Normal/Loop1" in Table 20-39.
Single byte data accesses in detail mode are always stored to the low byte of the trace buffer (CDATAL or
XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always
stored to trace buffer byte3 and the byte at the higher address is stored to byte2
Table 20-39. Trace Buffer Organization
Mode
8-Byte Wide Word Buffer
7 6 5 4 3 2 1 0
XGATE DETAIL CXINF1 CADRH1 CADRM1 CADRL1 XDATAH1 XDATAL1 XADRM1 XADRL1
CXINF2 CADRH2 CADRM2 CADRL2 XDATAH2 XDATAL2 XADRM2 XADRL2
CPU
DETAIL
CXINF1 CADRH1 CADRM1 CADRL1 CDATAH1 CDATAL1 XADRM1 XADRL1
CXINF2 CADRH2 CADRM2 CADRL2 CDATAH2 CDATAL2 XADRM2 XADRL2
Both
NORMAL
/ LOOP1
XINF0 XADRM0 XADRL0 CINF0 CADRH0 CADRM0 CADRL0
1
XINF1
1
COF in CPU only. XGATE trace buffer entries in this tracing step are invalid
CINF1 CADRH1 CADRM1 CADRL1
2
XINF2
2
COF in XGATE only. CPU trace buffer entries in this tracing step are invalid
XADRM2 XADRL2 CINF2
XGATE
NORMAL
/ LOOP1
XINF1 XADRM1 XADRL1 XINF0 XADRM0 XADRL0
XINF3 XADRM3 XADRL3 XINF2 XADRM2 XADRL2
CPU
NORMAL
/ LOOP1
CINF1 CADRH1 CADRM1 CADRL1 CINF0 CADRH0 CADRM0 CADRL0
CINF3 CADRH3 CADRM3 CADRL3 CINF2 CADRH2 CADRM2 CADRL2