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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
MC9S12XDP512 Data Sheet, Rev. 2.11
336 Freescale Semiconductor
7.3.2.10 ATD Status Register 2 (ATDSTAT2)
This read-only register contains the Conversion Complete Flags CCF15 to CCF8.
Read: Anytime
Write: Anytime, no effect
Table 7-20. Special Channel Select Coding
SC CD CC CB CA Analog Input Channel
1 0 0 X X Reserved
101 0 0 V
RH
101 0 1 V
RL
101 1 0 (V
RH
+V
RL
) / 2
1 0 1 1 1 Reserved
1 1 X X X Reserved
Module Base + 0x000A
76543210
R CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 CCF8
W
Reset 00000000
= Unimplemented or Reserved
Figure 7-12. ATD Status Register 2 (ATDSTAT2)
Table 7-21. ATDSTAT2 Field Descriptions
Field Description
7:0
CCF[15:8]
Conversion Complete Flag Bits — A conversion complete flag is set at the end of each conversion in a
conversion sequence. The flags are associated with the conversion position in a sequence (and also the result
register number). Therefore, CCF8 is set when the ninth conversion in a sequence is complete and the result
is available in result register ATDDR8; CCF9 is set when the tenth conversion in a sequence is complete and
the result is available in ATDDR9, and so forth. A flag CCFx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when
one of the following occurs:
• Write to ATDCTL5 (a new conversion sequence is started)
• If AFFC = 0 and read of ATDSTAT2 followed by read of result register ATDDRx
• If AFFC = 1 and read of result register ATDDRx
In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing
by methods B) or C) will be overwritten by the set.
0 Conversion number x not completed
1 Conversion number x has completed, result ready in ATDDRx