Chapter 21 Interrupt (S12MC9S12XDP512V1)
MC9S12XDP512 Data Sheet, Rev. 2.11
848
PRELIMINARY Freescale Semiconductor
NON-DISCLOSURE AGREEMENT REQUIRED
21.3.1 Register Descriptions
This section describes in address order all the XINT registers and their individual bits.
Address
Register
Name
Bit 7 654321Bit 0
0x0121 IVBR R
IVB_ADDR[7:0]
W
0x0126 INT_XGPRIO R 00000
XILVL[2:0]
W
0x0127 INT_CFADDR R
INT_CFADDR[7:4]
0000
W
0x0128 INT_CFDATA0 R
RQST
0000
PRIOLVL[2:0]
W
0x0129 INT_CFDATA1 R
RQST
0000
PRIOLVL[2:0]
W
0x012A INT_CFDATA2 R
RQST
0000
PRIOLVL[2:0]
W
0x012B INT_CFDATA3 R
RQST
0000
PRIOLVL[2:0]
W
0x012C INT_CFDATA4 R
RQST
0000
PRIOLVL[2:0]
W
0x012D INT_CFDATA5 R
RQST
0000
PRIOLVL[2:0]
W
0x012E INT_CFDATA6 R
RQST
0000
PRIOLVL[2:0]
W
0x012F INT_CFDATA7 R
RQST
0000
PRIOLVL[2:0]
W
= Unimplemented or Reserved
Figure 21-2. XINT Register Summary