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Chapter 20 Debug (S12XDBGV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 805
20.3.1.10 Debug State Control Register 3 (DBGSCR3)
Read: Anytime
Write: Anytime when DBG not armed.
This register is visible at 0x0027 only with COMRV[1]=1. The state control register 3 selects the targeted
next state while in State3. The matches refer to the match channels of the comparator match control logic
as depicted in Figure 20-1 and described in Section 20.3.1.11.1, “Debug Comparator Control Register
Table 20-22. DBGSCR2 Field Descriptions
Field Description
3–0
SC[3:0}
State Control Bits — These bits select the targeted next state while in State2, based upon the match event.
See Table 20-23.
The trigger priorities described in Table 20-38 dictate that in the case of simultaneous matches, the match on
the lower channel number ([0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final
state has priority over all other matches.
Table 20-23. State2 Sequencer Next State Selection
SC[3:0] Description
0000 Any match triggers to state1
0001 Any match triggers to state3
0010 Any match triggers to final state
0011 Match3 triggers to State1....... Other matches have no effect
0100 Match3 triggers to State3....... Other matches have no effect
0101 Match3 triggers to final state....... Other matches have no effect
0110 Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
0111 Match1 triggers to State3....... Match0 triggers final state....... Other matches have no effect
1000 Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
1001 Match2 triggers to State3....... Match0 triggers final state....... Other matches have no effect
1010 Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
1011 Match3 triggers to State3....... Match1 triggers final state....... Other matches have no effect
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
Unimplemented or Reserved
Figure 20-12. Debug State Control Register 3 (DBGSCR3)