Chapter 1 Device Overview (MC9S12XDP512V2)
MC9S12XDP512 Data Sheet, Rev. 2.11
36 Freescale Semiconductor
0x0030–0x0031 Module Mapping Control (S12XMMC) Map 3 of 4
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0030 PPAGE
R
PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
W
0x0031 Reserved
R00000000
W
0x0032–0x0033 Port Integration Module (PIM) Map 4 of 5
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0032 PORTK
R
PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0
W
0x0033 DDRK
R
DDRK7 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0
W
0x0034–0x003F Clock and Reset Generator (CRG) Map
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0034 SYNR
R0 0
SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
W
0x0035 REFDV
R
00
REFDV5 REFDV4 REFDV3 REFDV2 REFDV1 REFDV0
W
0x0036 CTFLG
R00000000
W Reserved For Factory Test
0x0037 CRGFLG
R
RTIF PORF LVRF LOCKIF
LOCK TRACK
SCMIF
SCM
W
0x0038 CRGINT
R
RTIE ILAF
0
LOCKIE
00
SCMIE
0
W
0x0039 CLKSEL
R
PLLSEL PSTP
00
PLLWAI
0
RTIWAI COPWAI
W
0x003A PLLCTL
R
CME PLLON AUTO ACQ FSTWKP PRE PCE SCME
W
0x003B RTICTL
R
RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
0x003C COPCTL
R
WCOP RSBCK
000
CR2 CR1 CR0
W
0x003D FORBYP
R00000000
W Reserved For Factory Test
0x003E CTCTL
R0000 000
W Reserved For Factory Test
0x003F ARMCOP
R00000000
W Bit 7 654321Bit 0