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Chapter 9 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 403
9.8.1.13 Index Register plus Register Offset (IDR)
For load and store instructions (RS, RI) provides a variable offset in a register.
Examples:
LDB R4,(R1,R2) ; loads a byte from R1+R2 into R4
STW R4,(R1,R2) ; stores R4 as a word to R1+R2
9.8.1.14 Index Register plus Register Offset with Post-increment (IDR+)
[RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory. In case
of a byte access the index register will be incremented by one. In case of a word access it will be
incremented by two.
Examples:
LDB R4,(R1,R2+) ; loads a byte from R1+R2 into R4, R2+=1
STW R4,(R1,R2+) ; stores R4 as a word to R1+R2, R2+=2
9.8.1.15 Index Register plus Register Offset with Pre-decrement (–IDR)
[RS, -RI] provides a variable offset in a register, which is decremented before accessing the memory. In
case of a byte access the index register will be decremented by one. In case of a word access it will be
decremented by two.
Examples:
LDB R4,(R1,-R2) ; R2 -=1, loads a byte from R1+R2 into R4
STW R4,(R1,-R2) ; R2 -=2, stores R4 as a word to R1+R2
9.8.2 Instruction Summary and Usage
9.8.2.1 Load & Store Instructions
Any register can be loaded either with an immediate or from the address space using indexed addressing
modes.
LDL RD,#IMM8 ; loads an immediate 8 bit value to the lower byte of RD
LDW RD,(RB,RI) ; loads data using RB+RI as effective address
LDB RD,(RB, RI+) ; loads data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation
The same set of modes is available for the store instructions
STB RS,(RB, RI) ; stores data using RB+RI as effective address
STW RS,(RB, RI+) ; stores data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation.