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Chapter 4 Port Integration Module (S12XDP512PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
178 Freescale Semiconductor
4.1.1 Features
A full-featured PIM module includes these distinctive registers:
• Data and data direction registers for Ports A, B, C, D, E, K, T, S, M, P, H, J, AD0, and AD1 when
used as general-purpose I/O
• Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,
H, and J on per-pin basis
• Control registers to enable/disable pull-up devices on Ports AD0, and AD1 on per-pin basis
• Single control register to enable/disable pull-ups on Ports A, B, C, D, E, and K on per-port basis
and on BKGD pin
• Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, AD0, and AD1
on per-pin basis
• Single control register to enable/disable reduced output drive on Ports A, B, C, D, E, and K on
per-port basis
• Control registers to enable/disable open-drain (wired-OR) mode on Ports S and M
• Control registers to enable/disable pin interrupts on Ports P, H, and J
• Interrupt flag register for pin interrupts on Ports P, H, and J
• Control register to configure
IRQ pin operation
• Free-running clock outputs
A standard port pin has the following minimum features:
• Input/output selection
• 5V output drive with two selectable drive strengths
• 5V digital and analog input
• Input with selectable pull-up or pull-down device
Optional features:
• Open drain for wired-OR connections
• Interrupt inputs with glitch filtering
• Reduced input threshold to support low voltage applications
4.1.2 Block Diagram
Figure 4-1 is a block diagram of the MC9S12XDP512.
• Signals shown in Bold are not available in 80-pin packages.
• Signals shown in Bold-Italics are neither available in 112-pin nor in 80-pin packages.
• Shaded labels denote alternative module routing ports.