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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 151
3.3.2.5 EEPROM Protection Register (EPROT)
The EPROT register defines which EEPROM sectors are protected against program or erase operations.
During the reset sequence, the EPROT register is loaded from the EEPROM Protection byte at address
offset 0x0FFD (see Table 3-1).All bits in the EPROT register are readable and writable except for
RNV[6:4] which are only readable. The EPOPEN and EPDIS bits can only be written to the protected
state. The EPS bits can be written anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, the
state of the EPDIS and EPS bits is irrelevant.
To change the EEPROM protection that will be loaded during the reset sequence, the EEPROM memory
must be unprotected, then the EEPROM Protection byte must be reprogrammed. Trying to alter data in any
protected area in the EEPROM memory will result in a protection violation error and the PVIOL flag will
be set in the ESTAT register. The mass erase of an EEPROM block is possible only when protection is
fully disabled by setting the EPOPEN and EPDIS bits.
Module Base + 0x0004
76543210
R
EPOPEN
RNV6 RNV5 RNV4
EPDIS EPS2 EPS1 EPS0
W
Reset F F F FFFFF
= Unimplemented or Reserved
Figure 3-6. EEPROM Protection Register (EPROT)
Table 3-5. EPROT Field Descriptions
Field Description
7
EPOPEN
Opens the EEPROM for Program or Erase
0 The entire EEPROM memory is protected from program and erase.
1 The EEPROM sectors not protected are enabled for program or erase.
6–4
RNV[6:4]
Reserved Nonvolatile Bits — The RNV[6:4] bits should remain in the erased state “1” for future enhancements.
3
EPDIS
EEPROM Protection Address Range Disable — The EPDIS bit determines whether there is a protected area
in a specific region of the EEPROM memory ending with address offset 0x0FFF.
0 Protection enabled.
1 Protection disabled.
2–0
EPS[2:0]
EEPROM Protection Address Size — The EPS[2:0] bits determine the size of the protected area as shown
inTable 3-6. The EPS bits can only be written to while the EPDIS bit is set.