Chapter 17 Voltage Regulator (S12VREG3V3V5)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 747
17.4.10.1 Low-Voltage Interrupt (LVI)
In FPM, VREG_3V3 monitors the input voltage V
DDA
. Whenever V
DDA
drops below level V
LVIA,
the
status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when V
DDA
rises above level V
LVID
.An
interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable
bit LVIE = 1.
NOTE
On entering the Reduced Power Mode, the LVIF is not cleared by the
VREG_3V3.
17.4.10.2 Autonomous Periodical Interrupt (API)
As soon as the configured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated
by flag APIF = 1, is triggered if interrupt enable bit APIE = 1.
Autonomous periodical interrupt (API) APIE = 1
Table 17-10. Interrupt Vectors
Interrupt Source Local Enable