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Chapter 4 Port Integration Module (S12XDP512PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
222 Freescale Semiconductor
4.3.2.30 Port M Data Register (PTM)
Read: Anytime.
Write: Anytime.
Port M pins 75–0 are associated with the CAN0, CAN1, CAN2, CAN3, SCI3, as well as the routed CAN0,
CAN4, and SPI0 modules. When not used with any of the peripherals, these pins can be used as general
purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
0x0250
76543210
R
PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
W
CAN TXCAN3 RXCAN3 TXCAN2 RXCAN2 TXCAN1 RXCAN1 TXCAN0 RXCAN0
Routed
CAN0
TXCAN0 RXCAN0 TXCAN0 RXCAN0
Routed
CAN4
TXCAN4 RXCAN4 TXCAN4 RXCAN4
Routed
SPIO
SCK0 MOSI0
SS0 MISO0
Reset 00000000
Figure 4-32. Port M Data Register (PTM)
Table 4-32. PTM Field Descriptions
Field Description
7–6
PTM[7:6]
The CAN3 function (TXCAN3 and RXCAN3) takes precedence over the CAN4, SCI3 and the general purpose
I/O function if the CAN3 module is enabled. Refer to MSCAN section for details.
The CAN4 function (TXCAN4 and RXCAN4) takes precedence over
the SCI3 and the general purpose I/O
function if the CAN4 module is enabled. Refer to MSCAN section for details.
The SCI3 function (TXD3 and RXD3) takes precedence over the general purpose I/O function if the SCI3 module
is enabled. Refer to SCI section for details.
5–4
PTM[5:4]
The CAN2 function (TXCAN2 and RXCAN2) takes precedence over the routed CAN0, routed CAN4, the routed
SPI0 and the general purpose I/O function if the CAN2 module is enabled{pim_9xd_prio.m}.
The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed CAN4, the routed SPI0
and the general purpose I/O function if the routed CAN0 module is enabled.
The routed CAN4 function (TXCAN4 and RXCAN4) takes precedence overthe routed SPI0 and general purpose
I/O function if the routed CAN4 module is enabled. Refer to MSCAN section for details.
The routed SPI0 function (SCK0 and MOSI0) takes precedence of the general purpose I/O function if the routed
SPI0 is enabled. Refer to SPI section for details.