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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.11
670 Freescale Semiconductor
14.4.8.1 Description of Interrupt Operation
The MSCAN supports four interrupt vectors (see Table 14-38), any of which can be individually masked
(for details see sections from Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register
(CANRIER),” to Section 14.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”).
NOTE
The dedicated interrupt vector addresses are defined in the Resets and
Interrupts chapter.
14.4.8.2 Transmit Interrupt
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
14.4.8.3 Receive Interrupt
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.
This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are
multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the
foreground buffer.
14.4.8.4 Wake-Up Interrupt
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCN internal sleep mode.
WUPE (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must be enabled.
14.4.8.5 Error Interrupt
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition
occurrs. Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG) indicates one of the following
conditions:
• Overrun — An overrun condition of the receiver FIFO as described in Section 14.4.2.3, “Receive
Structures,” occurred.
• CAN Status Change — The actual value of the transmit and receive error counters control the
CAN bus state of the MSCAN. As soon as the error counters skip into a critical range
(Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change,
which caused the error condition, is indicated by the TSTAT and RSTAT flags (see
Table 14-38. Interrupt Vectors
Interrupt Source CCR Mask Local Enable
Wake-Up Interrupt (WUPIF) I bit CANRIER (WUPIE)
Error Interrupts Interrupt (CSCIF, OVRIF) I bit CANRIER (CSCIE, OVRIE)
Receive Interrupt (RXF) I bit CANRIER (RXFIE)
Transmit Interrupts (TXE[2:0]) I bit CANTIER (TXEIE[2:0])