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Chapter 4 Port Integration Module (S12XDP512PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
202 Freescale Semiconductor
4.3.2.7 Port C Data Direction Register (DDRC)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
4.3.2.8 Port D Data Direction Register (DDRD)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
0x0006 (PRR)
76543210
R
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
W
Reset 00000000
Figure 4-9. Port C Data Direction Register (DDRC)
Table 4-10. DDRC Field Descriptions
Field Description
7–0
DDRC[7:0]
Data Direction Port C — This register controls the data direction for portC. When Port C is operating as a general
purpose I/O port, DDRC determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTC after changing the DDRC register.
0x0007 (PRR)
76543210
R
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
W
Reset 00000000
Figure 4-10. Port D Data Direction Register (DDRD)