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MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 373
Chapter 9
XGATE (S12XGATEV2)
9.1 Introduction
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the
MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the
transferred data and perform complex communication protocols.
The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s
interrupt load.
Figure 9-1 gives an overview on the XGATE architecture.
This document describes the functionality of the XGATE module, including:
• XGATE registers (Section 9.3, “Memory Map and Register Definition”)
• XGATE RISC core (Section 9.4.1, “XGATE RISC Core”)
• Hardware semaphores (Section 9.4.4, “Semaphores”)
• Interrupt handling (Section 9.5, “Interrupts”)
• Debug features (Section 9.6, “Debug Mode”)
• Security (Section 9.7, “Security”)
• Instruction set (Section 9.8, “Instruction Set”)
9.1.1 Features
The XGATE module includes these features:
• Data movement between various targets (i.e Flash, RAM, and peripheral modules)
• Data manipulation through built in RISC core
• Provides up to 112 XGATE channels
— 104 hardware triggered channels
— 8 software triggered channels
• Hardware semaphores which are shared between the S12X_CPU and the XGATE module
• Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer
• Software error detection to catch erratic application code