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Chapter 1 Device Overview (MC9S12XDP512V2)
MC9S12XDP512 Data Sheet, Rev. 2.11
52 Freescale Semiconductor
0x0150–
0x0153
CAN0IDAR0–
CAN0IDAR3
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0154–
0x0157
CAN0IDMR0–
CAN0IDMR3
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0158–
0x015B
CAN0IDAR4–
CAN0IDAR7
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x015C
–
0x015F
CAN0IDMR4–
CAN0IDMR7
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0160–
0x016F
CAN0RXFG
R FOREGROUND RECEIVE BUFFER
(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)
W
0x0170–
0x017F
CAN0TXFG
R
FOREGROUND TRANSMIT BUFFER
(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)
W
Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0xXXX0
Extended ID R ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
Standard ID R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
CANxRIDR0 W
0xXXX1
Extended ID R ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
Standard ID R ID2 ID1 ID0 RTR IDE=0
CANxRIDR1 W
0xXXX2
Extended ID R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
Standard ID R
CANxRIDR2 W
0xXXX3
Extended ID R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
Standard ID R
CANxRIDR3 W
0xXXX4
–
0xXXXB
CANxRDSR0–
CANxRDSR7
R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
0xXXXC CANRxDLR
R
DLC3 DLC2 DLC1 DLC0
W
0xXXXD Reserved
R
W
0xXXXE CANxRTSRH
R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
W
0xXXXF CANxRTSRL
R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
W
0xXX10
Extended ID R
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
CANxTIDR0 W
Standard ID R
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
W
0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0