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Chapter 22 External Bus Interface (S12XEBIV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 863
Table 22-1. External System Signals Associated with MC9S12XDP512
Signal I
1
/O
1
All inputs are capable of reducing input threshold level
EBI Signal
Multiplex
(T)ime
2
(F)unction
3
2
Time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated
time slot (in modes where applicable).
3
Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin
depending on configuration and reset state.
Description
Available in Modes
NS SS NX ES EX ST
RE O — — Read Enable, indicates external read access No No Yes No No No
ADDR[22:20] O T — External address No No Yes Yes Yes Yes
ACC[2:0] O — Access source No No No Yes Yes Yes
ADDR[19:16] O T — External address No No Yes Yes Yes Yes
IQSTAT[3:0] O — Instruction Queue Status No No No Yes Yes Yes
ADDR[15:1] O T — External address No No Yes Yes Yes Yes
IVD[15:1] O — Internal visibility read data (IVIS = 1) No No No Yes Yes Yes
ADDR0 O T F External address No No No Yes Yes Yes
IVD0 O Internal visibility read data (IVIS = 1) No No No Yes Yes Yes
UDS O — Upper Data Select, indicates external access
to the high byte DATA[15:8]
No No Yes No No No
LSTRB O — F Low Strobe, indicates valid data on DATA[7:0] No No No Yes Yes Yes
LDS O — Lower Data Select, indicates external access
to the low byte DATA[7:0]
No No Yes No No No
R/
W O — F Read/Write, indicates the direction of internal
data transfers
No No No Yes Yes Yes
WE O — Write Enable, indicates external write access No No Yes No No No
DATA[15:8] I/O — — Bidirectional data (even address) No No Yes Yes Yes Yes
DATA[7:0] I/O — — Bidirectional data (odd address) No No Yes Yes Yes Yes
EWAIT I — — External control for external bus access
stretches (adding wait states)
No No Yes No Yes No