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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 369
8.3.2.13.2 Right Justified Result Data
8.4 Functional Description
The ATD is structured in an analog and a digital sub-block.
8.4.1 Analog Sub-Block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies V
DDA
and V
SSA
allow to isolate noise of other MCU circuitry from the analog sub-block.
8.4.1.1 Sample and Hold Machine
The sample and hold (S/H) machine accepts analog signals from the external surroundings and stores them
as capacitor charge on a storage node.
The sample process uses a two stage approach. During the first stage, the sample amplifier is used to
quickly charge the storage node.The second stage connects the input directly to the storage node to
complete the sample for high accuracy.
When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw
their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the
analog power consumption.
The input analog signals are unipolar and must fall within the potential range of V
SSA
to V
DDA
.
Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H
Module Base + 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H
76543210
R
R
0
0
0
0
0
0
0
0
0
0
0
0
BIT 9 MSB
0
BIT 8
0
10-bit data
8-bit data
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L
Module Base + 0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L
76543210
R
R
BIT 7
BIT 7 MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
BIT 0
BIT 0
10-bit data
8-bit data
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)