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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 759
18.3.2.8 PIT Load Register 0 to 3 (PITLD0–3)
Read: Anytime
Write: Anytime
Module Base + 0x0008, 0x0009
151413 1211 109876543210
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
Reset 0000000000000000
Figure 18-11. PIT Load Register 0 (PITLD0)
Module Base + 0x000C, 0x000D
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R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
Reset 0000000000000000
Figure 18-12. PIT Load Register 1 (PITLD1)
Module Base + 0x0010, 0x0011
151413 1211 109876543210
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
Reset 0000000000000000
Figure 18-13. PIT Load Register 2 (PITLD2)
Module Base + 0x0014, 0x0015
151413 1211 109876543210
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
Reset 0000000000000000
Figure 18-14. PIT Load Register 3 (PITLD3)
Table 18-9. PITLD0–3 Field Descriptions
Field Description
15:0
PLD[15:0]
PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the
PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer
has counted down to zero the PTF time-out flag will be set and the register value will be loaded. The PFLT bits
in the PITFLT register can be used to immediately update the count register with the new value if an immediate
load is desired.