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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.11
642 Freescale Semiconductor
14.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Module Base + 0x0014 (CANIDMR0)
0x0015 (CANIDMR1)
0x0016 (CANIDMR2)
0x0017 (CANIDMR3)
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
Figure 14-21. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
Table 14-23. CANIDMR0–CANIDMR3 Register Field Descriptions
Field Description
7:0
AM[7:0]
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit