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Chapter 1 Device Overview (MC9S12XDP512V2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 27
Figure 1-1. MC9S12XD-Family Block Diagram
512/384/256/128/64-Kbyte Flash
32/20/16/14/10/8/4-Kbyte RAM
Enhanced Capture
RESET
EXTAL
XTAL
SCI0
4/2/1-Kbyte EEPROM
BKGD
R/
W/WE
MODB/TAGHI
XIRQ
ECLKX2/
XCLKS
CPU12X
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PLL
V
SSPLL
XFC
V
DDPLL
V
DDA
V
SSA
V
RH
V
RL
ATD0
IRQ
LSTRB/LDS/EROMCTL
ECLK
MODA/
RE/TAGLO
PA4
PA3
PA2
PA1
PA0
PA7
PA6
PA5
TEST
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR15
ADDR14
ADDR13
PB4
PB3
PB2
PB1
PB0
PB7
PB6
PB5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR7
ADDR6
ADDR5
PE3
PE4
PE5
PE6
PE7
PE0
PE1
PE2
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD03
PAD04
PAD05
PAD06
PAD07
PAD00
PAD01
PAD02
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3
IOC4
IOC5
PT3
PT4
PT5
PT6
PT7
PT0
PT1
PT2
RXD
TXD
MISO
MOSI
PS3
PS4
PS5
PS0
PS1
PS2
SCI1
RXD
TXD
PP3
PP4
PP5
PP6
PP7
PP0
PP1
PP2
SCK
SS
PS6
PS7
SPI0
IIC0
SDA
SCL
PJ2
CS1
PJ4
CS0
CAN0
RXCAN
TXCAN
PM1
PM0
CAN1
RXCAN
TXCAN
PM2
PM3
CAN2
RXCAN
TXCAN
PM4
PM5
PM6
PM7
KWH2
KWH6
KWH0
KWH7
KWH1
KWH3
KWH4
KWH5
PH3
PH4
PH5
PH6
PH7
PH0
PH1
PH2
KWJ0
KWJ1
PJ0 CS3
PJ1
DDRADDRB
PTAPTB
DDRE
PTE
DDRAD0 & AD0
PTT
DDRT
PTP
DDRP
PTS
DDRS
PTM
DDRM
PTH
DDRH
PTJ
DDRJ
V
DDR1,2
V
SSR1,2
Voltage Regulator 3-5 V
CAN4
RXCAN
TXCAN
MISO
MOSI
SCK
SS
SPI2
MISO
MOSI
SCK
SS
SPI1
KWP2
KWP6
KWP0
KWP7
KWP1
KWP3
KWP4
KWP5
KWJ2
KWJ4
Timer
Signals shown in Bold-Italics are neither available on the 112-pin nor on the 80-pin oackage option
Module to Port Routing
PWM2
PWM6
PWM0
PWM7
PWM1
PWM3
PWM4
PWM5
PWM
8-Bit PPAGE
IQSTAT2
IQSTAT0
IQSTAT1
ACC2
PK3
PK6
PK0
PK1
ADDR19
EWAIT
ADDR16
ADDR17
ADDR18
PTK
DDRK
PK2
ACC1
PK4
PK5
ADDR20
ADDR21
ROMCTL/EWAIT
PK7
ADDR22
V
RH
V
RL
V
DDA
V
SSA
V
RH
V
RL
ATD1
AN10
AN14
AN8
AN15
AN9
AN11
AN12
AN13
PAD11
PAD12
PAD13
PAD14
PAD15
PAD08
PAD09
PAD10
V
DDA
V
SSA
DDRAD1 & AD1
AN18
AN22
AN16
AN23
AN17
AN19
AN20
AN21
PAD19
PAD20
PAD21
PAD22
PAD23
PAD16
PAD17
PAD18
PC4
PC3
PC2
PC1
PC0
PC7
PC6
PC5
DATA12
DATA11
DATA10
DATA9
DATA8
DATA15
DATA14
DATA13
PD4
PD3
PD2
PD1
PD0
PD7
PD6
PD5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
DDRCDDRD
PTCPTD
SCI2
RXD
TXD
PJ6
PJ7
PJ5 CS2KWJ5
KWJ6
KWJ7
Non-Multiplexed External Bus Interface (EBI)
V
DDX1,2
V
SSX1,2
I/O Supply 3-5 V
VDDA
VSSA
Analog Supply 3-5 V
V
DDPLL
V
SSPLL
PLL Supply 2.5 V
Enhanced Multilevel
Interrupt Module
XGATE
Peripheral Co-Processor
V
DD1,2
V
SS1,2
Digital Supply 2.5 V
Signals shown in Bold are not available on the 80-pin package
Allows 4-MByte
Program space
SCI3
RXD
TXD
SCI4
RXD
TXD
SCI5
RXD
TXD
IIC1
SDA
SCL
Timer
4-Channel
16-Bit with Prescaler
for Internal Timebases
CAN3
RXCAN
TXCAN
ADDR0UDS
IQSTAT3
ACC0
Single-Wire
Background
Debug Module
V
DDR
Voltage Regulator
V
SSR
V
DD1,2
V
SS1,2
V
REGEN
Clock
and Reset
Generation
Module