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Chapter 16 Serial Peripheral Interface (S12SPIV4)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 713
16.2 External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect
off chip. The MC9S12XDP512 module has a total of four external pins.
16.2.1 MOSI — Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data
when it is configured as slave.
16.2.2 MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
16.2.3 SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
16.2.4 SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
16.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
The memory map for the MC9S12XDP512 is given in Table 16-1. The address listed for each register is
the sum of a base address and an address offset. The base address is defined at the SoC level and the address
offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved
bits have no effect.
16.3.1 Module Memory Map
Table 16-1. MC9S12XDP512V4 Memory Map
Address Use Access
0x___0 SPI Control Register 1 (SPICR1) Read / Write
0x___1 SPI Control Register 2 (SPICR2) Read / Write
1
1
Certain bits are non-writable.
0x___2 SPI Baud Rate Register (SPIBR) Read / Write
1
0x___3 SPI Status Register (SPISR) Read
2
2
Writes to this register are ignored.
0x___4 Reserved —
23
0x___5 SPI Data Register (SPIDR) Read / Write
0x___6 Reserved —
23
0x___7 Reserved —
23