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Chapter 1 Device Overview (MC9S12XDP512V2)
MC9S12XDP512 Data Sheet, Rev. 2.11
76 Freescale Semiconductor
PH7 KWH7
SS2 TXD5 — V
DDR
PERH/PPSH Disabled Port H I/O, interrupt, SS of
SPI2, TXD of SCI5
PH6 KWH6 SCK2 RXD5 — V
DDR
PERH/
PPSH
Disabled Port H I/O, interrupt, SCK of
SPI2, RXD of SCI5
PH5 KWH5 MOSI2 TXD4 — V
DDR
PERH/
PPSH
Disabled Port H I/O, interrupt, MOSI
of SPI2, TXD of SCI4
PH4 KWH4 MISO2 RXD4 — V
DDR
PERH/PPSH Disabled Port H I/O, interrupt, MISO
of SPI2, RXD of SCI4
PH3 KWH3 SS1 — — V
DDR
PERH/PPSH Disabled Port H I/O, interrupt, SS of
SPI1
PH2 KWH2 SCK1 — — V
DDR
PERH/PPSH Disabled Port H I/O, interrupt, SCK of
SPI1
PH1 KWH1 MOSI1 — — V
DDR
PERH/PPSH Disabled Port H I/O, interrupt, MOSI
of SPI1
PH0 KWH0 MISO1 — — V
DDR
PERH/PPSH Disabled Port H I/O, interrupt, MISO
of SPI1
PJ7 KWJ7 TXCAN4 SCL0 TXCAN0 V
DDX
PERJ/
PPSJ
Up Port J I/O, interrupt, TX of
CAN4, SCL of IIC0, TX of
CAN0
PJ6 KWJ6 RXCAN4 SDA0 RXCAN0 V
DDX
PERJ/
PPSJ
Up Port J I/O, interrupt, RX of
CAN4, SDA of IIC0, RX of
CAN0
PJ5 KWJ5 SCL1
CS2 — V
DDX
PERJ/
PPSJ
Up Port J I/O, interrupt, SCL of
IIC1, chip select 2
PJ4 KWJ4 SDA1
CS0 — V
DDX
PERJ/
PPSJ
Up Port J I/O, interrupt, SDA of
IIC1, chip select 0
PJ2 KWJ2
CS1 — — V
DDX
PERJ/
PPSJ
Up Port J I/O, interrupt, chip
select 1
PJ1 KWJ1 TXD2 — — V
DDX
PERJ/
PPSJ
Up Port J I/O, interrupt, TXD of
SCI2
PJ0 KWJ0 RXD2
CS3 — V
DDX
PERJ/
PPSJ
Up Port J I/O, interrupt, RXD of
SCI2
PK7
EWAIT ROMCTL — — V
DDX
PUCR Up Port K I/O, EWAIT input,
ROM on control
PK[6:4] ADDR
[22:20]
ACC[2:0] — — V
DDX
PUCR Up Port K I/O, extended
addresses, access source
for external access
PK3 ADDR19 IQSTAT3 — — V
DDX
PUCR Up Extended address, PIPE
status
PK2 ADDR18 IQSTAT2 — — V
DDX
PUCR Up Extended address, PIPE
status
PK1 ADDR17 IQSTAT1 — — V
DDX
PUCR Up Extended address, PIPE
status
Table 1-3. Signal Properties Summary (Sheet 2 of 4)
Pin
Name
Function 1
Pin
Name
Function 2
Pin
Name
Function 3
Pin
Name
Function 4
Pin
Name
Function 5
Power
Supply
Internal Pull
Resistor
Description
CTRL
Reset
State