Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description
MC9S12XDP512 Data Sheet, Rev. 2.11
598 Freescale Semiconductor
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 13-4, all subsequent tap points are separated by 2
IBC5-3
as shown in the
tap2tap column in Table 13-4. The SCL Tap is used to generated the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 13-5.
0102964
0116968
100 14 17 14 16
101 30 33 30 32
110 62 65 62 64
111 126 129 126 128
Table 13-5. Multiplier Factor
IBC7-6 MUL
00 01
01 02
10 04
11 RESERVED
IBC5-3
(bin)
scl2start
(clocks)
scl2stop
(clocks)
scl2tap
(clocks)
tap2tap
(clocks)
SCL Divider
SDA Hold
SCL
SDA