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Chapter 1 Device Overview (MC9S12XDP512V2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 25
• Five 1 M bit per second, CAN 2.0 A, B software compatible modules
— Five receive and three transmit buffers
— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit
— Four separate interrupt channels for Rx, Tx, error, and wake-up
— Low-pass filter wake-up function
— Loop-back for self-test operation
• ECT (enhanced capture timer)
— 16-bit main counter with 7-bit prescaler
— 8 programmable input capture or output compare channels
— Four 8-bit or two 16-bit pulse accumulators
• 8 PWM (pulse-width modulator) channels
— Programmable period and duty cycle
— 8-bit 8-channel or 16-bit 4-channel
— Separate control for each pulse width and duty cycle
— Center-aligned or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
— Fast emergency shutdown input
— Usable as interrupt inputs
• Serial interfaces
— Six asynchronous serial communication interfaces (SCI) with additional LIN support and
selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width
— Three Synchronous Serial Peripheral Interfaces (SPI)
• Two IIC (Inter-IC bus) Modules
— Compatible with IIC bus standard
— Multi-master operation
— Software programmable for one of 256 different serial clock frequencies
• On-Chip Voltage Regulator
— Two parallel, linear voltage regulators with bandgap reference
— Low-voltage detect (LVD) with low-voltage interrupt (LVI)
— Power-on reset (POR) circuit
— 3.3-V–5.5-V operation
— Low-voltage reset (LVR)
— Ultra low-power wake-up timer
• 144 -pin LQFP, 112-pin LQFP, and 80-pin QFP packages
— I/O lines with 5-V input and drive capability
— Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation
— 5-V A/D converter inputs
— Operation at 80 MHz equivalent to 40-MHz bus speed