Chapter 9 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 387
9.3.2.7 XGATE Condition Code Register (XGCCR)
The XGCCR register (Figure 9-9) provides access to the RISC core’s condition code register.
Read: In debug mode if unsecured
Write: In debug mode if unsecured
Module Base +0x001D
76543210
R0000
XGN XGZ XGV XGC
W
Reset 00000000
= Unimplemented or Reserved
Figure 9-9. XGATE Condition Code Register (XGCCR)
Table 9-8. XGCCR Field Descriptions
Field Description
3
XGN
Sign Flag — The RISC core’s Sign flag
2
XGZ
Zero Flag — The RISC core’s Zero flag
1
XGV
Overflow Flag — The RISC core’s Overflow flag
0
XGC
Carry Flag — The RISC core’s Carry flag