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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.11
628 Freescale Semiconductor
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in Table 14-8 and Table 14-9).
Eqn. 14-1
14.3.2.5 MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
NOTE
The CANRFLG register is held in the reset state
1
when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable again
as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
Read: Anytime
Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are
read-only; write of 1 clears flag; write of 0 is ignored.
Table 14-9. Time Segment 1 Values
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1
0 0 0 0 1 Tq clock cycle
1
1
This setting is not valid. Please refer to Table 14-36 for valid settings.
0 0 0 1 2 Tq clock cycles
1
0 0 1 0 3 Tq clock cycles
1
0 0 1 1 4 Tq clock cycles
:::: :
1 1 1 0 15 Tq clock cycles
1 1 1 1 16 Tq clock cycles
Module Base + 0x0004
76543210
R
WUPIF CSCIF
RSTAT1 RSTAT0 TSTAT1 TSTAT0
OVRIF RXF
W
Reset: 00000000
= Unimplemented
Figure 14-7. MSCAN Receiver Flag Register (CANRFLG)
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
Bit Time
Prescaler value()
f
CANCLK
------------------------------------------------------
1 TimeSegment1 TimeSegment2++()•=