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1. SUMMARY
(5) Number of SSCNET lines (address 020001h)
bit1 bit0 Content
0 0 1 line
0 1 2 lines
1 0 Reserved
1 1 Reserved
(6) Signal during interrupt output (address 020004h)
bit1 bit0 Content
0 0 Interrupts are not generated
0 1 During interrupt output
(7) Interrupt signal clear register (1CH) (address 020008h)
bit1 bit0 Content
0 0 Invalid
0
1 1CH interrupt signal is cleared