Filter
Top Products
EXPANDED MCS-48 SYSTEM
keep boundary crossings
to
a minimum.
Jumping
to
subroutines across the boundary
should be avoided when possible since the
programmer must keep track
of
which bank
to
return
to
after completion
of
the subrou-
tine.
If these subroutines are to be nested and
accessed from either bank, a software
"stack"
should
be
implemented
to
save the bank
switch bit just
as
if
it were another bit
of
the
program counter.
From a hardware standpoint bank switching
is very straight-forward and
involves only the
connection of an
I/O liile or lines as bank
enable signals. These enables are ANDed
with
normal memory and I/O chip select
signals
to activate the proper bank.
3.6 Control Signal Summary
The
following
table summarizes the
in-
structions
which
activate the various
control
outputs
of
the MCS-48 processors.
CONTROL
WHEN ACTIVE
SIGNAL
RD
DURING
MOVX
A,@R
OR
INS
BUS
WR
DURING
MOVX
@R,A
OR
OUTL
BUS
ALE
EVERY MACHINE CYCLE
PSEN
DURING FETCH
OF
EXTERNAL
PROGRAM MEMORY(INSTRUCTION
OR
IMMEDIATE DATA)
PROG
DURING MOVD A,P
ANLD
P,A
MOVD P,A
ORLD
P,A
During
all
other
instructions
these
outputs
are driven
to
the inactive state.
3.7 Port Characteristics
BUS Port Operations
The
BUS
port
can operate in three
different
modes:
as
a latched 1/0 port,
as
a
bi-
directional bus port,
or
as a program
memo-
ry address
output
when external
memory
is
3·11
used. The BUS port lines are
either
active
high, active
low,
or
high impedance (float-
ing).
The latched mode (INS,
OUTU
is intended
for
use in the single
chip
configuration
where BUS
is
not being used as an expan-
der
port.
OUTL
and MOVX
instructions
can
be mixed
if
necessary. However, a previous-
ly latched
output
will
be
destroyed
by
exe-
cuting
a MOVX instruction and BUS
will
be
left in the high impedance state. INS does
not
put
the BUS in a high
impedance
state.
Therefore, the use
of
MOVX
after
OUTL
to
put
the BUS in a high
impedance
state is
necessary before an
INS
instruction
in-
tended
to
read an external
word
(as
op-
posed
to
the previously latched value).
OUTL
should never
be
used in a system
with
external program memory, since
latch-
ing BUS can cause the
next
instruction,
if
external,
to
be fetched
improperly.
Port 2 Operations
The
lower
half
of
Port 2 can be used in three
different
ways:
as
a quasi,
bi-directional
static port,
as
an 8243 expander port, and
to
address external program memory. In all
cases
outputs
are driven
low
by
an active
device and driven high
momentarily
by
an
active device and
held
high
by
a
50Kfl
resistor
to
+5V.
The
port
may contain latched 1/0 data
prior
to
its use in another mode
without
affecting
operation
of
either. If
lower
Port 2 (P20-3) is
used
to
output
address
for
an external
program
memory
fetch
the
1/0
information
previously latched will be
automatically
removed
temporarily
while
address is
present then restored when the fetch
is
complete. However,
if
lower
Port 2 is used
to
communicate
with an 8243, previously
latched
1/0
information
will
be removed
and
not
restored. After an
input
from
the
8243
P20-3
will be left in
the
input
mode
(floating).
After
an
output
to
the
8243
P20-3
will
contain
the value written, ANDed,
or
ORed
to
the 8243 port.