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't
t
SINGLE COMPONENT SYSTEM
interrupt operations.
As
in any CALL
to
sub-
routine, the Program Counter and Program
Status
word
are saved in the stack. For a
description
of
this operation
see
the previous
section, Program Counter and
Stack. Pro-
gram Memory location 3 usually contains
an
unconditional
jump
to
an
interrupt service
subroutine
elsewhere in program memory.
The end
of
an
interrupt service subroutine is
signalled by the execution
of
a Return and
Restore
Status instruction
RETR.
The inter-
rupt system
is
single
level
in that once
an
inter-
rupt is detected all further interrupt requests
are ignored
until execution
of
an
RETR
re-
enables
the interrupt input logic. This occurs
at the beginning
of
the second cycle of the
RETR
instruction. This sequence holds true
also for
an
internal interrupt generated by
timer
overflow. If
an
internal timer/counter
generated interrupt and
an
external interrupt
are detected at the same time, the
external
source will
be
nicognized.
See
the following
Timer/Counter section for a description
of
timer interrupt. If heeded, a second external
interrupt can
b,e
cr~ated
by enabling the
timer/counter
i'1terrupt, loading
FFH
in the
Counter (one
less than terminal count), and
enabling the event counter mode. A
"1"
to
"0"
transition on the
T1
input will then cause
an
interrupt vector
to
location
7.
Interrupt
Timing
The interrupt input may
be
enabled or disabled
under Program Control using the
EN
I and
DIS I instructions. Interrupts are disabled by
Reset and remain so
until enabled by the
users program. An.interrupt request must
be
removed before the RETR instruction is ex-
ecuted upon return from the service routine
otherwise the processor
will re-enter the ser-
vice routine immediately. Many peripheral
devices prevent this situation by resetting
their interrupt request
line whenever the pro-
cessor accesses (Reads or Writes) the periph-
erals
data buffer register. If the interrupting
device does not require access by the
pro-
cessor, one output line of the 8048 may be
designated as an "interrupt
acknowledge"
which
is
activated by the service subroutine to
reset the interrupt request. The
INT pin may
2·8
also be tested using the conditional jump
instruction
JNI. This instruction may
be
used
to detect the presence of a pending interrupt
before interrupts are
enabled. If interrupt is
left disabled,
iNT
may be used as another test
input
like
TO
and
T1.
2.1.10
Timer/Counter
The
8048 contains a counter to aid the user
In
counting external events and generating ac-
curate time delays without placing a burden
on the processor for these functions.
In
both
modes the counter operation is the same, the
only difference being the source of the input
to the counter.
Counter
The 8-bit up binary counter
is
presettable
and
readable with two MOV instructions which
transfer the contents of
the accumulator to the
cou nter
and
vice
versa.
The cou nter content
is
not affected by
Reset
and
is
initialized solely
by the MOV T,A instruction. The counter
is
stopped by a Reset or STOP TCNT instruction
and
rer;nains
stopped until started
as
a timer
by a
START T instruction or as an event
counter'
by
a START CNT instruction. Once
started the counter will increment to its maxi-
mum count (FF) and overflow to zero contin-
uing its count until stopped by a STOP TCNT
instruction or Reset.
The increment from maximum count to zero
(overflow) results
in
the setting of
an
overflow
flag flip-flop
and in the .generation of an
interrupt request. The state of the
overflow
flag
is testable with the conditional jump
instruction
JTF.
The flag is reset by executing
a JTF or
by
Reset. The interrupt request
is
stored
in
a latch and then ORed with the
external interrupt input
iNT.
The timer interrupt
may be
enabled or di$at:>ledindependently of
external interrupt by the
EN
TCNTI and DIS
TCNTI
instructions. If enabled, the counter
overflow will cause a subroutine call
to
location
7 where the timer or counter service routine
may be stored.
If timer and external interrupts
occur
simultaneously, the external source will
be
recognized and the Call will be to location
3.
Since the timer interrupt is latched it will
remain pending until the external device. is