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EXPANDED MCS-48 SYSTEM
Interconnection
to
the_8048
lL
very
straightforward with BUS,
RD,
and WR con-
necting
directly to the corresponding pins on
the 8255. The
only design consideration is the
way in which the
internal registers of the 8255
are to be addressed.
If
the registers are to be
addressed as
external data memory using the
MOVX instructions, the appropriate number of
address bits
(in
this case,
2)
must be latched
on BUS using ALE as described in the section
on
external data memories. If only a single
device is connected to BUS, the 8255 may be
continuously selected by grounding CS. If
multiple
8255's are used, additional address
bits can be
latched and used as chip selects.
A second addressing method eliminates ex-
ternal latches
and
chip select decoders by
using output port
lines as address and chip
select lines directly. This method, of course,
requires the setting of
an
output port with ad-
dress information prior to executing a MOVX
instruction.
3.4 Multi-Chip MCS-48 Systems
The accompanying figure shows the addition
of two memory expanders to the 8048, one
8355/8755
ROM and one 8156 RAM. The
main consideration in designing such a sys-
tem is the addressing of the various memories
and
I/O ports. Note that in this configuration
address
lines
A,o
and
A"
have been ORed to
chip
select the 8355. This ensures that the
chip is active for
all external program memory
fetches
in
the 1 K
to
3K range and is disabled
for all other addresses. This gating has been
added to
allow the I/O port of the 8355 to be
used.
If the chip was left selected all the time
there
would be conflict between these ports
and the RAM and
I/O
of the 8156. The
NOR
gate could
be
eliminated
and~"
connected
directly to the
CE
(instead of CE) input of the
8355; however, this
would create a
1K
word
"hole"
in
the program memory
by
causing the
8355 to
be
active in the 2K to 4K range in-
stead of the
normal 1 K to 3K range.
8156/8355
8048
THE
THREE
COMPONENT
MCS-48 SYSTEM
3-9
PORT
A
PORT
B
PORT
C
---TIMER
OUT