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MICROPROCESSOR
INTERFACE
GPIS TRIGGER OUTPU
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~
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...!!.
2-
---.!
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2-
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T2
8291
r1L
DO
Di01
01 0102
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02
0103
30
D!
0104
31
04
0105
32
05
0106
33
06
0107
34
07 0'108
35
CS
OAV
36
Rii
Tlih
1
WR ATN
26
INT
EOI
39
CLOCK TiR2
2
RESET NOAC
38
OREQ
NRFO
37
OACK
SRQ
27
TRIG
lIEN
25
iFC
24
, = GPIS SUS TRANSCEIVER
Figure
7.
8291
and 8293 System Configuration
8293
25
23
10
9
8
7
6
5
24
1
~
--.!.
3
~
1
2
10
9
8
6
5
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8293
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0104
0104'
0105
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TIRl
OPTA
ATN OPTS
EOI
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6293
EOI
EOI'
ATN
ATN'
TIRl
TIR2
NOAC
NOAC'
NRFO
NRFO'
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SRQ'
lIEN
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IFC
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OPTA
OPTS
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r1L
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~
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