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8259A
PROGRAMMABLE INTERRUPT
CONTROLLER
•
MCS·86™ Compatible
•
Programmable Interrupt Modes
•
MCS·80185™ Compatible
•
Individual Request Mask Capability
•
Elght·Level Priority Controller
• Single
+ 5V Supply (No Clocks)
•
Expandable to 64 Levels
• 28·Pin Dual·ln·Line
Package
The Intell!l 8259A Programmable Interrupt Controller handles up
to
eight vectored priority interrupts for the
CPU.
It is
cas cad
able for up
to
64
vectored priority interrupts without additional circuitry. It is packaged in a 28-pin
DIP,
uses
NMOS technology
and
requires a single + 5V
supp!y_
Circuitry
is
static, requiring
no
clock input.
The 8259A is designed
to
minimize the software and real time overhead in handling mUlti-level priority interrupts_ It has
several modes, permitting optimization for a variety
of
system requirements.
The 8259A is
fully upward compatible with the
Intel<i>
8259.
Software originally written for the
8259
will operate the
8259A in
all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).
PIN CONFIGURATION
CS
iVA
AD
0,
0,
Os
0,
0,
0,
D,
0,
CASO
D7·~.~L
AD
iVA
Ao
cs
CASI
GND
vee
Au
INTA
IR7
IRG
IR5
IR4
IR3
IR2
IRI
IRO
INT
SP/EN
CAS2
PIN NAMES
DATA
BUS
IBI-DIRECTIONALI
READ
INPUT
--.~-----
._".
WRITE
INPUT
COMMAND
SELECT ADDRESS
CHIP
SELECT
CAS2-CASO
CASCADE
LINES
_________
_
!lI'/£I'J
SLAVE PROGRAM INPUT/ENABLE
INT
IRO-IR7
__
'NT~!l.uPT
OU!!.l!!.
___
_
INTERRUPT
ACKNOWLEDGE
INPUT
INTERRUPT REaUEST
INPUTS
WR-
cs -
CAS1
_
CAS2
...
--
DATA
BUS
BUFFER
BLOCK DIAGRAM
INTA INT
'INTERNAL
BUS
INTEL
CORPORAmlN
ASSUMES
NO
RESPONSIBILITY
FOR
THE
US[
Of
ANY
CIRCUITRY
OTHER
THAN
CIRCUITRY
EIIIIOOlEO
IN
AN
INTEL
PRODUCT.
NO
OTHER
CIRCUIT
PATENT
LICENSES
ARE
IMPlIEO.
"
INTEL
CORPORATION.
1979
9-38
-IRO
-IR1