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Symbol
ALE
(
Inputl
ADo-7
(
Inputl
AS-1o
Iinputl
CE1
CE2
(
Inputl
10iM
(
Inputl
RD
(Inputl
lOW
(
Input
I
8355/8355-2
Function
When ALE (Address
latch
Enable is
high, ADo-7,
101M,
AS-1o,
CE, and CE
enter
address latched. The signals
I AD,
101M,
AS-1o,
CE, CE I are latched
in at the
trailing
edge
of
ALE.
Bidirectional
AddresslData
bus. The
lower
8-bits
of
the ROM
or
1/0
address
are
applied to the bus lines when ALE
is high.
During
an
1/0
cycle, Port A
or
Bare
selected based
on
the
latched value
of
ADo. It RD
or
lOR is
low
when
the
latched
chip
enables are active, the
output
buffers present data
on
the
bus.
These are the
high
order
bits
of
the
ROM
address.
They
do
not
affect
1/0
oper-
ations.
Chip
Enable Inputs:
CE1
is active
low
and
CE2
is
active~.
The
8355 can be
accessed
only
when
BOTH
Ghip En-
ables are active at the
time
the
ALE
signal latches
them
up. It
either
Chip
Enab!e
input
is
not
active,
the
ADo-7
and READY
outputs
will be in a high
impedance
state.
It the latched
10/M
is
high
when RD is
low, the
output
data
comes
from
an
1/0 port. It
it
is
low
the
output
data
comes from the
ROM.
It the latched
Chip
Enables are active
when RD goes
low,
the
ADo-7
output
buffers are enabled and
output
either
the selected ROM
location
or
1/0
port.
When both RD and
lOR are high,
the
ADo-7
output
buffers
are 3-state.
It the latched
Chip
Enables are active,
a
low
on
lOW
causes
the
output
port
pointed
to
by
the latched value
of
ADo
to be written
with
the
data on ADo-7.
The state
of
101M is ignored.
6-70
Symbol
ClK
(lnputl
READY
(Outputl
PAO-7
(I
nput!
Output
I
PBO-7
(Input!
Outputl
RESET
(
Input)
lOR
(Input)
Vee
Vss
Function
The
ClK
is used to
force
the
READY
into
its
high
impedance
state
after
it
has been
forced
low
by CE low, CE
high
and ALE high.
Ready is a 3-state
output
controlled
by
CEL
CE2,
ALE and
ClK.
READY is
forced
low
when
the
Chip
Enables are
active
during
the
time
ALE is high, and
remains
low
until the rising
edge
of
the
next
ClK
(see Figure
61.
These are general
purpose
1/0
pins.
Their
input!output
direction
is
deter-
mined
by
the
contents
of
Data
Direction
Register (DDRI.
Port
A is selected
for
write
operations
when the
Chip
Enables
are active and
iOW
is
low
and a 0 was
previously
latched
from
ADo.
Read
operation
is selected
by
either
lOR
low
and active
Chip
Enables and
ADo
low,
Q[
101M high, RD low, active
chip
enables, and ADo low.
This
general
purpose
1/0
port
is
identical
to
Port
A
except
that
it
is
selected
by
a 1 latched from ADo.
An
input
high
on RESET causes all
pins
in
Port
A and B
to
assume
input
mode.
When
the
Chip
Enables are active, a
low
on lOR will
output
the
selected
1/0
port
onto
the
AD
bus. lOR
low
performs
the
same
function
as
the
combination
101M
high
and RD low. When lOR is
not
used
in a system,
lOR
should
be tied
to
Vee
("1").
+5
volt
supply.
Ground
Reference.