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108048/8748/8035L
PIN DESCRIPTION
Designation Pin #
Function
Designation
Pin
#
Function
VSS
20 Circuit GND potential
RD
8
Output
strobe activated during a
Voo
26
Programming power supply; +25V
B
US
read. Can be used
to
enable
during program, +5V during oper·
data
onto
the
bus from an external
ation for
both
ROM
and PROM.
device.
low
power standby pin
in
8048
Used
as
a read strobe
to
external
and
8035l.
data
memory. (Active low)
Vee
40
Main
power supply; +5V during
RESET
4
Input which
is
used
to
initialize
the
operation and programming.
processor.
Also used during PROM
PROG
25
Program
pulse (+23V) input pin
programming verification, and
during
8748
programming.
power down. (Active
low)
Output
strobe for
8243
I/O
(Non TTL
VIH
)
expander.
WR
10
Output
strobe during a bus write.
P10·P17
27·34
8-bit quasi-bidirectional port.
(Active
low)
Port 1
Used
as
write ·strobe
to
external
P20-P27 21-24
8-bit quasi-bidirectional port.
data memory.
Port 2
35-38
P20-P23 contain
the
four high
ALE
11
Address latch enable. This signal
order program counter bits during
occurs once during each
cycle and
an
external program memory fetch
is
useful as a clock
output.
and
serve as a 4-bit I/O expander
bus for 8243.
The negative edge
of
ALE strobes
DBo-DB7
12-19
True
bidirectional
port
which can
address into
external
data
and pro-
gram memory.
BUS
be written or read synchronously
PSEN
9
Program store
enable. This
output
using
the
RD,
WR
strobes. The
port
can also be statically latched.
occurs
only
during a fetch
to
exter-
Contains
the
8 low order program
nal program memory. (Active low)
counter bits during an external
55
5 Single step input can be used in con-
program memory
fetch, and receives
junction with ALE
to
"single
step"
the
addressed instruction under
the
the
processor through each
in-
control of P5EN. Also contains
the
struction. (Active low)
address and data during
an
external
EA
7
External access input which forces
RAM
data store instruction, under
all program memory fetches
to
re-
control
of
ALE, RD, and WR.
ference
external memory, Useful
TO
Input pin testable using
the
con-
for
emulation and debug, and
ditional transfer instructions
JTO
essential
for
testing and program
and
JNTO.
TO
can be designated as
verification. (Active high)
a
clock
output
using
ENTO
ClK
XTAL1 2 One side
of
crystal
input
for inter-
instruction.
TO
is
also used during
nal oscillator. Also input for exter-
programming.
nal source. (Non TTL VIH)
T1
39
Input pin testable using
the
JT1,
XTAl2
3
Other side
of
crystal input.
and JNT1 instructions. Can be des-
ignated
the
timer/counter
input using
the
STRT CNT instruction.
INT
6
Interrupt input. Initiates an inter-
rupt
if
interrupt
is
enabled. Inter-
rupt
is
disabled after a reset. Also
testable
with conditional jump
instruction. (Active
low)
6-19