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SINGLE
COMPONENT
SYSTEM
impedance device
(-
5KO) is switched in
momentarily
(-
500ns) whenever a "1" is
written to the
line. When a "0"
is
written to the
line a
low
impedance
(-3000)
device over-
comes the
light pullup and provides
TTL
current sinking capability. Since the pulldown
transistor is a low impedance device a "1"
must first be written to any line which is to be
used as
an
input. Reset initializes all lines to
the high impedance
"1" state. This structure
allows input and output on the same pin and
also allows a mix of input lines and output
lines
on
the same port. The quasi-bidirectional
port
in
combination with the ANL and ORL
logical
instructions provide
an
efficient means
for
handling single line inputs and outputs
within
an
8-bit
processor. See also Section
3.7.
Bus
,.
Bus is also
an
8-bit port
~hich
is a true bi-
directional
port with associated input and
output strobes.
If the bidirectional feature is
not needed,
Bus
can serve
as
either a statically
latched
output port or non-latching input port.
Input and output lines
on
this port cannot be
mixed however.
As a static port, data is written and
latched
using the OUTL instruction and inputted using
the
INS
instruction. The
INS
and
OUTL instruc-
tions
generate
pulses on the corresponding
RD
and WR output strobe lines; however,
in
the static port mode they are generally not
used.
As
a bidirectional port the MOVX instruc-
tions are used to read and write the port. A
write to the port generates a
pulse on the WR
output line and output data is valid at the
trailing edge
of
WR. A read
of
the port
generates a
pulse on the
RD
output line and
input data must be
valid at the trailing edge of
RD.
When not being written or read, the BUS
lines
are in a high impedance state. See also
Sections
3.6 and 3.7.
2.1.5 Test and
INT
Inputs
Three pins serve
as
inputs and are testable
with the conditional jump instruction. These
are
TO,
T1,
and
INT.
These pins allow inputs
2-5
to cause program branches without the neces-
sity to load
an
input port into the accumulator.
The
TO,
T1,
and
INTpins
have other possible
functions
as
well. See the pin description
in
Sec. 2.2.
2.1.6 Program
Counter
and
Stack
The
Program
Counter
is
an independent
counter
while the Program
Counter
Stack is
implemented using pairs
of
registers in the
Data Memory Array.
Only
10 (or
11)
bits
of
the Program
Counter
are used
to
address
the
1024
(2048)
words
of
on-board program
memory
while the most
significant
bits are
used
for
external Program
Memory
fetches.
The
Program
Counter
is initialized
to
zero
by activating the Reset
line.
An
interrupt or CALL to a subroutine causes
the contents of the program counter to be
stored
in
one of the 8 register pairs of the
Program Counter
Stack. The pair to be used
is
determined by a 3-bit Stack Pointer which
is part of the Program
Status Word (PSW).
Data
RAM
locations 8 thru 23 are available
as
stack registers and are used to store the
Program Counter and 4 bits
of
PSW as
shown in the figure. The
Stack Pointer when
initialized to 000 points to RAM locations
8 and
9.
The first subroutine jump or interrupt
results
in
the program counter contents being
transferred to locations 8 and 9 of the
RAM
array.
The stack pointer
is
then incremented
by one to
pOint
to locations
10
and
11
in
anticipation of another CALL. Nesting of
sub-
routines within subroutines can continue up to
8 times without
overflowing the stack. If
overflow
does occur the deepest address
stored (location 8 and
9)
will be overwritten
and
lost since the stack pointer overflows
from
111
to 000.
It
also underflows from 000
to
111.
The end of a subroutine, which is Signalled by
a return
instruction (RET or RETR). causes
the
Stack Pointer to be decremented and the
contents of the
resulting register pair to be
transferred to
the Program Counter.