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8XC196NP, 80C196NU USER’S MANUAL
4-12
4.5.1 Using Registers
The 256-byte lower register file contains the CPU special-function registers and the stack pointer.
The remainder of the lower register file and all of the upper register file is available for your use.
Peripheral special-function registers (SFRs) and memory-mapped SFRs reside in higher memory.
The peripheral SFRs can be windowed into the lower register file for direct access. Memory-
mapped SFRs cannot be windowed; you must use indirect or indexed addressing to access them.
All SFRs can be operated on as BYTEs or WORDs, unless otherwise specified. See “Peripheral
Special-function Registers (SFRs)” on page 5-7 and “Register File” on page 5-9 for more infor-
mation.
To use these registers effectively, you must have some overall strategy for allocating them. The
C programming language adopts a simple, effective strategy. It allocates the eight or sixteen bytes
beginning at address 1CH as temporary storage and treats the remaining area in the register file
as a segment of memory that is allocated as required.
NOTE
Using any SFR as a base or index register for indirect or indexed operations
can cause unpredictable results because external events can change the
contents of SFRs. Also, because some SFRs are cleared when read, consider
the implications of using an SFR as an operand in a read-modify-write
instruction (e.g., XORB).
4.5.2 Addressing 32-bit Operands
The 32-bit operands (DOUBLE-WORDs and LONG-INTEGERs) are formed by two adjacent
16-bit words in memory. The least-significant word of a DOUBLE-WORD is always in the lower
address, even when the data is in the stack (which means that the most-significant word must be
pushed into the stack first). The address of a 32-bit operand is that of its least-significant byte.
The hardware supports the 32-bit data types as operands in shift operations, as dividends of 32-
by-16 divide operations, and as products of 16-by-16 multiply operations. For these operations,
the 32-bit operand must reside in the lower register file and must be aligned at an address that is
evenly divisible by four.
4.5.3 Addressing 64-bit Operands
The hardware supports the QUAD-WORD only as the operand of the EBMOVI instruction. For
this operation, the QUAD-WORD variable must reside in the lower register file and must be
aligned at an address that is evenly divisible by eight.