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I/O PORTS
Figure 7-3. EPORT Structure
Vcc
Q2
Q1
EP_REG
EP_MODE
Sample
Latch
PH1 Clock
Internal Bus
EP_PIN
DQ
0
1
Vcc
Vcc
Weak
Pullup
Medium
Pullup
RESET#
Q3
Q4
Buffer
Vss
Read Port
LE
300ns Delay
I/O Pin
Address Bit from
Address MUX
EP_DIR
POWERDOWN#
IDLE#
HOLD#
RESET#
DATA
A0241-02
R1
150Ω to 200Ω