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INTERFACING WITH EXTERNAL MEMORY
Figure 13-24. Deferred Bus-cycle Mode Timing Diagram (80C196NU)
T
LHLH
+ 2t
T
WHLH
+ 2t
T
RHLH
+ 2t
T
AVRL
+ 2t
T
AVDV
+ 2t
T
AVWL
+ 2t
valid
valid
valid
CLKOUT
ALE
RD#
AD15:0
WR#
AD15:0
BHE#, INST
A19:16
CS
x
#
T0010-02
(read)
(write)