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8XC196NP, 80C196NU USER’S MANUAL
Index-8
Power consumption, reducing, 2-12, 12-7
Powerdown mode, 2-12, 12-7–12-12
circuitry, external, 12-11
controlling, 13-15
disabling, 12-6, 12-7
enabling, 12-7
entering, 12-6, 12-7
exiting, 12-8, 12-11
with EXTINT, 12-8–12-12
with RESET#, 12-8
Prefetch queue, 2-5, 5-23
Priority encoder, 6-4
Priority, instruction fetch versus data fetch, 5-23
Processor status word‚ See PSW
Product information, ordering, 1-6
Program counter‚ See PC
Program memory, 5-2, 5-5, 5-25
PSW, 2-4, 4-13, 6-12, C-25
flags, and instructions, A-5
PTS, 2-4, 2-6, 6-1
and EPA, 6-26–6-36
block transfer mode, 6-23
control block, See PTSCB
cycle execution time, 6-10
cycle, defined, 6-23
instructions, A-59, A-67
interrupt latency, 6-9
interrupt processing flow, 6-2
PWM modes, 6-26–6-36
PWM remap mode, 6-32
PWM toggle mode, 6-27, 10-13, 10-14, 10-15
routine, defined, 6-1
single transfer mode, 6-20
vectors, memory locations, 5-6, 5-7
See also PWM
PTSCB, 6-1, 6-4, 6-7, 6-18, 6-23
memory locations, 5-7
PTSSEL, 6-7, 6-10, 6-18
PTSSRV, 6-7, 6-18
Pulse-width modulator, See PWM
PUSH instruction, A-3, A-34, A-51, A-55, A-62
PUSHA instruction, A-2, A-35, A-52, A-55, A-62
PUSHF instruction, A-2, A-35, A-52, A-55, A-62
PWM, 6-26, 9-1
and cascading timer/counters, 10-6
block diagram, 9-1
calculating duty cycle, 6-26
calculating frequency, 6-26
clock prescaler, 9-4
D/A converter, 9-10
duty cycle, 9-5
enabling outputs, 9-9
generating, 10-15
generating analog outputs, 9-9
modes, 6-26–6-36
output period, 9-3
overview, 9-1
programming duty cycle, 9-5
remap mode, 6-32
toggle mode, 6-27
typical waveforms, 9-5
waveform, 6-27
with dedicated timer/counter, 10-15
See also EPA‚ PTS
PWM0, 9-9
PWM0_CONTROL, C-51, C-54
PWM1, 9-9
PWM1_CONTROL, C-51, C-54
PWM2, 9-9
PWM2:0, 9-9, B-10
PWM2_CONTROL, C-51, C-54
Q
QUAD-WORD, defined, 4-4
Quick reference guides, ordering, 1-8
R
RALU, 2-4–2-5, 5-11
RAM, internal
register RAM, 5-11
RD#, 13-4, 13-36, B-10
during bus hold, 13-30
READY, 13-4, 13-26–13-30, B-10
after reset, 13-18
for CCB fetches, 13-17
timing requirements, 13-27
Ready control, 13-26–13-30
REAL variables, 4-5
Register bits
naming conventions, 1-4
reserved, 1-4
Register file, 2-3, 5-9
and windows, 5-10, 5-13
lower, 5-10, 5-11, 5-13
upper, 5-10, 5-11