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6-35
STANDARD AND PTS INTERRUPTS
Figure 6-18 shows the EPA and PTS operations for this example. The first timer match occurs at
time = 0 for EPA0, which asserts the output and generates an interrupt.
PWM Remap Cycle 1. The PTS adds T2 to EPA0_TIME and toggles the TBIT.
The output remains asserted until the second timer match occurs at T1 for EPA1, which deasserts
the output and generates an interrupt.
PWM Remap Cycle 2. The PTS adds T2 to EPA1_TIME and toggles the TBIT.
Alternating EPA0 and EPA1 interrupts continue, with EPA0 asserting the output and EPA1 deas-
serting it.
Register Location Function
PTSCON PTSCB + 1 PTS Control Bits
M2:0 PTS Mode
These bits specify the PTS mode:
M2 M1 M0
010PWM
TMOD Remap Mode Select
0 = PWM remap mode
TBIT Toggle Bit Initial Value
Defines the initial value of TBIT.
1 = selects initial value as one
0 = selects initial value as zero
NOTE: In PWM remap mode, the TBIT value is not used;
PTSCONST1 is always added to the PTSPTR1 value.
However, the unused TBIT still toggles at the end of
each PWM remap cycle. Reading this bit returns the
current value of TBIT.
PTS PWM Remap Mode Control Block (Continued)
Figure 6-17. PTS Control Block — PWM Remap Mode (Continued)