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8XC196NP, 80C196NU USER’S MANUAL
A-58
Conditional Jump
Mnemonic
Direct Immediate Indirect
Indexed
(Notes 1, 2)
Length Opcode Length Opcode Length Opcode
Length
S/L
Opcode
DJNZ ——————3/—E0
DJNZW ——————3/—E1
JBC ——————3/—30–37
JBS ——————3/—38–3F
JC ——————2/—DB
JE ——————2/—DF
JGE ——————2/—D6
JGT ——————2/—D2
JH ——————2/—D9
JLE ——————2/—DA
JLT ——————2/—DE
JNC ——————2/—D3
JNE ——————2/—D7
JNH ——————2/—D1
JNST ——————2/—D0
JNV ——————2/—D5
JNVT ——————2/—D4
JST ——————2/—D8
JV ——————2/—DD
JVT ——————2/—DC
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as
S
/
L
, where
S
is the short-indexed
instruction length and
L
is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.