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A-57
INSTRUCTION SET REFERENCE
Jump
Mnemonic
Direct Immediate Extended-indirect
Extended-
indexed
Length Opcode Length Opcode Length Opcode Length Opcode
EBR ———— 2E3——
EJMP ——————4E6
Mnemonic
Direct Immediate
Indirect
(Note 1)
Indexed
(Notes 1, 2)
Length Opcode Length Opcode Length Opcode
Length
S/L
Opcode
BR ———— 2E3——
LJMP ———————/3E7
SJMP (Note 3) ——————2/—20–27
TIJMP 4 E2 4 E2 — — —/4 E2
Call
Mnemonic
Direct Immediate Extended-indirect
Extended-
indexed
Length Opcode Length Opcode Length Opcode Length Opcode
ECALL ——————4F1
Mnemonic
Direct Immediate
Indirect
(Note 1)
Indexed
(Note 1)
Length Opcode Length Opcode Length Opcode Length Opcode
LCALL —————— 3EF
RET ————1F0——
SCALL (Note 3) ——————228–2F
TRAP 1F7——————
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as
S
/
L
, where
S
is the short-indexed
instruction length and
L
is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.