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C-19
REGISTERS
EPA_PEND
EPA_PEND
Address:
Reset State:
1F9EH
AAH
When hardware detects a pending EPA3:0 overrun interrupt (OVR3:0), it sets the corresponding bit in
the EPA interrupt pending (EPA_PEND) register. OVR0 and OVR1 are multiplexed to share one bit
(OVR0_1) in the INT_PEND1 register. Similarly, OVR2 and OVR3 are multiplexed to share another bit
(OVR2_3) in the INT_PEND1 register.
7 0
— OVR3 — OVR2 — OVR1 — OVR0
Bit
Number
Function
7, 5, 3, 1 Reserved. These bits are undefined.
6, 4, 2, 0 Any set bit indicates that the corresponding overrun interrupt source is pending.
NOTE: This register was called EPA_STAT in previous documentation for the 8XC196NP.