Filter
Top Products
8XC196NP, 80C196NU USER’S MANUAL
A-16
EBMOVI EXTENDED INTERRUPTABLE BLOCK
MOVE. Moves a block of word data from one
memory location to another. This instruction
allows you to move blocks of up to 64K words
between any two locations in the 16-Mbyte
address space. This instruction is inter-
ruptable.
The source and destination addresses are
calculated using the extended indirect with
autoincrement addressing mode. A quad-
word register (PTRS) addresses the 24-bit
source and destination pointers, which are
stored in adjacent double-word registers. The
source pointer (SRCPTR) is the low double-
word and the destination pointer is the high
double-word of PTRS. A word register
(CNTREG) specifies the number of transfers.
The blocks of data can reside anywhere in
memory, but should not overlap.
COUNT
← (CNTREG)
LOOP: SRCPTR
← (PTRS)
DSTPTR
← (PTRS + 2)
(DSTPTR)
← (SRCPTR)
(PTRS)
← SRCPTR + 2
(PTRS + 2)
← DSTPTR + 2
COUNT
← COUNT 1
if COUNT
≠ 0 then
go to LOOP
PTRS, CNTREG
EBMOVI prt2_reg, wreg
(11100100) (wreg) (prt2_reg)
NOTES: The pointers are autoincre-
mented during this instruction.
However, CNTREG is decre-
mented only when the instruc-
tion is interrupted. When
EBMOVI is interrupted,
CNTREG is updated to store
the interim word count at the
time of the interrupt. For this
reason, you should always
reload CNTREG before starting
an EBMOVI.
For 20-bit addresses, the offset
must be in the range of
+524287 to –524288.
PSW Flag Settings
ZNCVVTST
——————
EBR EXTENDED BRANCH INDIRECT. Continues
execution at the address specified in the
operand word register. This instruction is an
unconditional indirect jump to anywhere in
the 16-Mbyte address space.
EBR shares its opcode (E3) with the BR
instruction. To differentiate between the two,
the compiler sets the least-significant bit of
the EBR instruction. For example: EBR [50]
becomes E351 when compiled.
PC
← (DEST)
DEST
EBR cadd
or
EBR [treg]
(11100011) (treg)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
PSW Flag Settings
ZNCVVTST
——————
Table A-6. Instruction Set (Continued)
Mnemonic Operation Instruction Format